1. Field of the Invention
The present invention relates to integrated circuits, and, in particular, to field programmable gate arrays.
2. Description of the Related Art
FIG. 1 shows a block diagram of a conventional field programmable gate array (FPGA) 100, consisting of an array of programmable logic cells (PLCs) 102 surrounded by a ring of programmable input/output (I/O) cells (PICs) 104. The PICs handle the flow of data into and out of the PLC array, which may be programmed by a user to implement a desired set of operations.
FIG. 2 shows a more detailed schematic diagram of part of conventional FPGA 100 of FIG. 1. FIG. 2 shows four PICs that correspond to two adjacent columns in the PLC array. PIC 202 and PIC 204 are the top and bottom PICs, respectively, for column i in the PLC array, while PIC 206 and PIC 208 are the top and bottom PICs, respectively, for column i+1 in the PLC array. Each PIC has four pads (e.g., 210) connected to the inputs of a four-to-one mux (e.g., 212). For each PIC, the output of the mux is connected to a global-signal spine (e.g., 214) that carries global signals from the PIC to perpendicular branches (e.g., 216) that correspond to rows in the PLC array and provide programmable connections to the individual PLCs (not shown in FIG. 2). Analogously, but not represented in FIG. 2, FPGA 100 also has left and right PICs that drive horizontal spines that are programmably connected to vertical branches in the same manner as shown in FIG. 2 for the vertical spines and horizontal branches of FPGA 100. The horizontal and vertical spines and corresponding vertical and horizontal branches provide the flexibility in FPGA 100 to access any PLC from any pad of any PIC.
According to conventional FPGA design, each spine 214 is unidirectional. For example, spine 214 can only be driven downward from PIC 202, while spine 218 which can only be driven upward from PIC 204. In order to provide access to each branch from each PIC, each vertical spine may be programmably connected directly to each horizontal branch, and each horizontal spine may be programmably connected directly to each vertical branch. Each programmable connection adds capacitance to the spine, which slows down the speed at which the PIC can transmit global signals to the PLCs. Moreover, in conventional FPGA designs, only one of the two spines that correspond to a given column of PLCs can drive onto a given branch at a time. Thus, when PIC 202 drives the downward spine 214 for column i in FPGA 100 and spine 214 then drives branch 216, PIC 204 can drive the upward spine 218, but spine 218 cannot drive onto branch 216.